Bottom Line
A triple capacity-expansion cycle (TSMC + memory big-three + supply chain) kicks in 2026–2028. Korean and Japanese suppliers with 50%+ category share capture revenue-proportional upside.
Reading depth
- 01 TSMC 2nm + the Advanced Packaging Capacity ExplosionIn the AI era the fastest-growing semiconductor segment is not the leading process node but CoWoS/SoIC advanced packaging.Jump to section
- 02 Memory Big-Three Capacity Expansion — the 2026–2028 Simultaneous RampKorea's two memory makers hold near-term leadership in global AI memory supply while Micron takes US domestic supply from 2030 onward.Jump to section
- 03 The Suppliers' Triple Order Cycle — Transmission MechanismFoundry, memory, and overseas-fab channels activate simultaneously, compounding equipment-and-materials orders beyond any single channel.Jump to section
- 04 Korea's First-Wave Beneficiary CategoriesKorea's primary supply-chain beneficiaries concentrate in TC bonders (Hanmi Semiconductor) and high-pressure annealing (HPSP), both with 50%+ share.Jump to section
- 05 Japan's First-Wave Beneficiary CategoriesJapan holds six categories with 50%+ share or a duopoly, giving it broader supply-chain exposure to the cycle than Korea.Jump to section
- 06 Conclusion — Monitoring the Cycle's Peak and DownturnThe AI capex cycle is a quadruple accumulation of foundry, memory, packaging, and overseas fabs, with its peak to be verified in the 2027–2028 window.Jump to section
01 TSMC 2nm + the Advanced Packaging Capacity Explosion
1.1 What five 2nm fabs running at once means
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[Figure 1] TSMC's five 2nm fabs running simultaneously — full capacity in 2026
TSMC 2nm (N2) volume production started at Kaohsiung Fab 22 in Q4 2025 and enters full capacity expansion in 2026. The five fabs running in 2026 are Fab 20 and Hsinchu 2 (adjacent to R&D) in the Hsinchu cluster, plus Fab 22, Kaohsiung 2, and Kaohsiung 3 in the Kaohsiung cluster. First-year wafer output at +45% versus the 2023 first year of 3nm matters a great deal — it signals that TSMC is investing in 2nm capacity far more aggressively than it did at the 3nm introduction.
The direct driver of this acceleration is AI accelerator demand. With NVIDIA's Vera Rubin architecture adopting the 2nm + HBM4 + -L combination, a single customer has pre-locked more than 50% of TSMC's 2nm capacity. AMD's MI400 series and the ASICs of AWS, Google, Meta, and Microsoft are converging on 2nm as well. Five 2nm fabs running at once is not a single-scenario bet — it is a response to simultaneous demand surges from five to seven hyperscale players.
1.2 CAGR by process and packaging — is fastest
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[Figure 2] TSMC capacity expansion CAGR by process and packaging
Comparing the capacity CAGRs TSMC has officially guided reveals a telling pattern. 2nm is very steep at a 70% CAGR for 2026–2028, but advanced packaging is faster. CoWoS runs at an 80%+ CAGR and SoIC at 90%+ over 2022–2027. 3nm grows at a 25% CAGR over the same period — roughly a third to a quarter of packaging's pace. The implication is clear — the fastest-growing area of the AI-era semiconductor value chain is not the leading-edge process but advanced packaging.
| Item | Period | CAGR | Meaning |
|---|---|---|---|
| 2nm capacity | 2026–2028 | 70% | Acceleration into full volume production |
| 3nm capacity | 2022–2027 | 25% | Stable growth in maturity |
| CoWoS capacity | 2022–2027 | 80%+ | Core of NVIDIA·AMD AI accelerators |
| SoIC capacity | 2022–2027 | 90%+ | Bound for NVIDIA Rubin·Feynman |
Item
2nm capacity
- Period
- 2026–2028
- CAGR
- 70%
- Meaning
- Acceleration into full volume production
Item
3nm capacity
- Period
- 2022–2027
- CAGR
- 25%
- Meaning
- Stable growth in maturity
Item
CoWoS capacity
- Period
- 2022–2027
- CAGR
- 80%+
- Meaning
- Core of NVIDIA·AMD AI accelerators
Item
SoIC capacity
- Period
- 2022–2027
- CAGR
- 90%+
- Meaning
- Bound for NVIDIA Rubin·Feynman
SoIC is steepest at 90%+ because NVIDIA's Rubin Ultra (2027) and next-generation Feynman (2028) architectures are set to adopt SoIC as their core packaging technology. SoIC uses copper-to-copper hybrid bonding for 3D vertical stacking, dramatically raising transistor density. per 10K wafers of SoIC capacity runs about $6.8–7.0B — far more capital-intensive per unit of capacity than CoWoS. A 90% SoIC CAGR combined with that capital intensity creates the largest order surge in the entire advanced-packaging equipment market.
1.3 Overseas fabs accelerate together — Arizona +80%, Kumamoto +130%
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[Figure 3] TSMC overseas fab capacity — steep growth in both the US and Japan
2026 is the inflection point for TSMC's overseas fab expansion. Arizona Fab 1 output rises +80% in 2026 versus 2025; Kumamoto Fab 1 in Japan rises +130%. Add the additional $100B US investment (five more plants) announced on March 4, 2025 under Trump-administration pressure, and TSMC's US capacity traces its steepest cumulative growth curve over 2026–2030.
Overseas fab acceleration matters greatly for Korean and Japanese suppliers. Every new overseas TSMC fab brings global shipping, qualification, and localization of materials, parts, and equipment — and Korean suppliers (notably Hanmi Semiconductor and HPSP) and Japanese suppliers (notably DISCO and Tokyo Electron) already have proven global supply-chain relationships, making them direct beneficiaries of the revenue expansion. The Arizona advanced-packaging facility in particular ramps in earnest in 2027–2028, which makes 2025–2026 the window when its equipment orders concentrate.