TPU, Trainium, MI400 — no custom AI silicon reaches tape-out without these two companies' design software
Cadence and Synopsys are the two design gates an AI chip must pass through. Every custom silicon is designed on top of these two companies' software, and the more complex AI makes chips, the higher the cost of passing through. The two are now converting that complexity back into their own revenue via AI-EDA (agentic design automation). Two questions remain: the single binary risk of China export controls, and how much the AI design boom is already priced into the two stocks.
Cadence's fiscal Q1 2026 revenue hit $1.474B (+19% YoY) with a record backlog of $8.0B, and it raised full-year guidance to +17%. Synopsys closed its $35B acquisition of Ansys and guided FY2026 revenue to $9.61B (midpoint), with Design Automation now 83% of revenue. As both companies competitively unveiled agentic EDA at Computex 2026 (Cadence Cerebrus/ChipStack, Synopsys.ai), design software emerged as a new investment axis in AI infrastructure.
Design power — Cadence (strong in digital, verification, hardware emulation; organic EDA growth) and Synopsys (#1 in IP and Design Automation; multiphysics expansion via Ansys). Market companions — custom-silicon fabless players (Broadcom, Marvell) and every hyperscaler's in-house chip. Offsets — China export controls (Cadence ~12% revenue exposure, Synopsys ~16%; a 2025 Cadence DOJ fine of $140M), the long-term possibility of AI-native design tools compressing EDA value, and an already-embedded valuation.
Chip design in one sentence: turning a circuit in your head into manufacturable mask data. sits in between.
The process is long. Synthesize the circuit into logic gates, place those gates on the chip, route them with wiring, and verify the timing holds, the power doesn't leak, and no physical rules are violated. At the end, the design must pass sign-off — the final verification before manufacturing — to move to the foundry. This entire flow runs on EDA tools.
Why can't a human do it? Scale. A modern AI chip holds tens of billions of transistors. No one places them one by one. Algorithms do. Those algorithms are EDA.
The key is accuracy. Foundries demand extreme precision of sign-off tools, because a design the tool passes must work in real silicon. A single tape-out at a leading node costs tens of millions of dollars. Get it wrong and that money is gone. So chip companies use only proven EDA tools. That is the first reason newcomers struggle to enter.
Tape-out is a stage reached only by passing through EDA tools. For a chip to become silicon, it must travel over Cadence's or Synopsys's software.
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