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Higher HBM Mix, Safer Stock? — How Base Die Logic Migration Shifts AI Memory Margin to Foundries

From HBM4, the base die becomes a leading-edge logic chip. Part of AI memory's value migrates from the three memory makers to foundries. The same 'HBM mix' hides different profit structures at Samsung, SK Hynix, and Micron

HHaelangdal·Founder AnalystJuly 5, 202620 min readThematic Deep Dive
Bottom Line

HBM4 is the first generation in memory history to split off the base die as a leading-edge logic chip. From that moment, part of HBM's value migrates from the three memory makers to foundries. SK Hynix and Micron cede that share to TSMC; only Samsung Electronics keeps it in-group through its own foundry — an expensive bet carrying a pricier node and yield risk.

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Reader's Brief — 30-second TL;DR

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Why Now

The variables to confirm are Samsung's 4nm/2nm yield curves, TSMC's base die pricing policy, and Micron's 2027 TSMC ramp. Samsung formalized its vertical integration roadmap at the July 1 SAFE Forum, and the July 2 rout (Samsung -9.1%, SK Hynix -14.6%) followed by the July 3 rebound forced a re-grading of the market's one-phrase 'HBM mix' arithmetic.

Winners ?? Losers

Beneficiaries: TSMC (new base die value inflow), Samsung Electronics (margin retained in group + foundry utilization and the 2028 profit path). Transmission: SK Hynix (the leader with roughly 70% of NVIDIA HBM4, but part of base die value booked externally), Micron (TSMC reliance grows from HBM4E). Pressure: if yield does not come together, Samsung's vertical integration becomes a cost, not a moat.

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Reading depth

1. The Hole in the Conventional Wisdom

The market's arithmetic is simple. Commodity DRAM is volatile; is high-margin demand locked to AI. So the higher a company's HBM mix, the safer it is. So far, correct.

The hole lies in the implicit assumption that memory makers capture all of the HBM margin. Through HBM3E, that was true. Both the core dies and the base die were fabbed by the memory maker on the same DRAM process. There was nowhere for value to leak.

HBM4 breaks that assumption. The HBM4 standard finalized by JEDEC (the semiconductor standards body), JESD270-4, specifies a 2,048-bit , up to 2TB/s per stack, and doubles the channel count from 16 to 32. To handle that bandwidth, the base at the bottom of the stack can no longer be a simple wiring board. It becomes a leading-edge logic chip carrying compute, test, and power management. And leading-edge logic is foundry territory.

Here is the crux. HBM4 is the first generation to split the processes — core die on DRAM nodes, base die on leading-edge logic nodes. From that moment on, the single phrase "HBM mix" starts to blend memory margin with foundry margin.

From HBM4 onward, two different companies' margins live inside the words "HBM mix."

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This report is provided for informational purposes only and does not constitute a recommendation to buy or sell any financial instrument. Investment decisions should be made based on your own judgment and responsibility. The analysis and opinions contained herein are based on information available at the time of writing and are subject to change.

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