The Big Three's legacy DRAM/NAND retreat is an irreversible structural pivot — a cycle where China's CXMT/YMTC and Taiwan's Nanya fill the void while Korean second-tier beneficiaries emerge.
Who Fills the Void — Screening Korean Value Chain Second-Tier Beneficiaries
The Big Three's legacy DRAM/NAND retreat is an irreversible structural pivot — a cycle where China's CXMT/YMTC and Taiwan's Nanya fill the void while Korean second-tier beneficiaries emerge.
Supply gaps of DDR4 -60-70%, LPDDR4/4X -40-50%, and MLC NAND -41.7% YoY for 2026-2027 are locked in; HBM conversion costs make a Big Three return economically irrational.
Beneficiaries — Korea (SK Hynix and Samsung HBM margin defense, SME suppliers, Jeju Semicon fabless), Taiwan (Nanya vertical integration), China (CXMT and YMTC share gains). Pressure — initial legacy spot price decline pressure.
Quarterly CXMT/YMTC DDR4 yield disclosures and spot price changes — Chinese follower yields surpassing 70% would signal easing of the supply shock.
Memory splits into two categories. DRAM is the "workbench" — short-term memory that holds what you're doing right now, disappearing when power is off. NAND is the "warehouse" — long-term memory that stores photos, videos, and apps.
DRAM varies by generation. DDR3 (legacy PC/server), (current mainstream, being discontinued), DDR5 (transitioning to mainstream), LPDDR4/4X (mid-low smartphones, Samsung EOL 2026), LPDDR5/5X (flagship), and HBM3E/HBM4 (AI accelerators). HBM is "ultra-high-speed DRAM" — stacked 8/12/16 high with 1,024 data lanes.
| Generation | Primary Use | Max Speed | Status |
|---|---|---|---|
| DDR4 | Current PC/server mainstream | 3.2 Gbps | EOL in progress (2026) |
| DDR5 | Latest PC/server | 6.4 Gbps | Mainstream transition |
| LPDDR4/4X | Mid-low smartphones | 4.3 Gbps | Samsung EOL 2026 |
| LPDDR5/5X | Flagship smartphones | 8.5 Gbps | Mainstream product |
| HBM3E | AI accelerators (NVIDIA H/B200) | 1,229 GB/s | Market core |
| HBM4 | Next-gen AI GPU | 2,000 GB/s | Volume ramp 2026 |
The key tension: one HBM stack requires 2–3x the wafer capacity of standard DRAM. The more HBM produced, the less commodity DRAM remains. All three players chose to reallocate finite fab capacity to HBM (3–5x margin) — commodity DRAM has physically become a scarce product.
NAND structure is layered too. SLC (1bit/cell, industrial), MLC (2bit, Samsung EOL June 2026), TLC (3bit, current mainstream), QLC (4bit, growing in AI server SSDs), PLC (5bit, development). The Big 3 are winding down MLC and concentrating on high-layer 3D TLC/QLC.
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